Delay-Insensitive Cell Matrix
نویسندگان
چکیده
This paper describes the design of a delay-insensitive (DI) Cell Matrix. This architecture allows for massively parallel, self-determined operation and can be used to implement regular digital circuits or new types of circuits for nanocomputing systems. One advantage of this cell matrix compared to its synchronous counterpart is the delay-insensitive asynchronous nature. This architecture does not need a global clock, which would be infeasible for nanocomputing systems due to the enormous number of clocked nodes. Instead, a handshaking protocol for inter-component communication is implemented. Keywords-parallel processing; asynchronous; delay-insensitive; clockless; NCL
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